Semiconductor device

ABSTRACT

A semiconductor device includes: a first semiconductor layer of first conductivity type; a second semiconductor layer of first conductivity type provided on the first semiconductor layer; a first semiconductor region of second conductivity type provided on the second semiconductor layer; a second semiconductor region of first conductivity type provided on the first semiconductor region; a first electrode provided in a first trench, the first trench reaching the second semiconductor layer from above the first semiconductor region, the first electrode facing the first semiconductor region via a first insulating film; a second electrode provided in a second trench, the second trench reaching the second semiconductor layer from above the first semiconductor region, the second electrode facing the first semiconductor region via a second insulating film; a third electrode including a first electrode portion, a second electrode portion provided on the first electrode portion and a third electrode portion provided on the second electrode portion, the first electrode portion being provided between the first trench and the second trench, the first electrode portion reaching the first semiconductor region from above the second semiconductor region, the first electrode portion being electrically connected to the first semiconductor region and the second semiconductor region; a third semiconductor region provided between the third electrode and the second semiconductor region provided between the first insulating film and the third electrode, the third semiconductor region having a higher concentration of impurities of second conductivity type than the first semiconductor region; a fourth semiconductor region provided between the third electrode and the second semiconductor region provided between the second insulating film and the third electrode, the fourth semiconductor region having a higher concentration of impurities of second conductivity type than the first semiconductor region; and a fifth semiconductor region provided between the first semiconductor region and the third electrode, the fifth semiconductor region being provided apart from the third semiconductor region and the fourth semiconductor region, the fifth semiconductor region having a higher concentration of impurities of second conductivity type than the first semiconductor region.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of application Ser. No. 17/007,241filed Aug. 31, 2020 and is based upon and claims the benefit of priorityfrom Japanese Patent Application No. 2020-050005, filed on Mar. 19,2020, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor device.

BACKGROUND

A semiconductor device such as a metal oxide semiconductor field effecttransistor (MOSFET) is used for power conversion and the like. Such asemiconductor device desirably has high reliability.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic cross-sectional view of a semiconductor deviceaccording to a first embodiment;

FIG. 2 is a schematic cross-sectional view of a main part of thesemiconductor device according to the first embodiment;

FIG. 3 is a schematic cross-sectional view illustrating a process ofmanufacturing the semiconductor device according to the firstembodiment;

FIG. 4 is a schematic cross-sectional view illustrating the process ofmanufacturing the semiconductor device according to the firstembodiment;

FIG. 5 is a schematic cross-sectional view illustrating the process ofmanufacturing the semiconductor device according to the firstembodiment;

FIG. 6 is a schematic cross-sectional view illustrating the process ofmanufacturing the semiconductor device according to the firstembodiment;

FIG. 7 is a schematic cross-sectional view illustrating the process ofmanufacturing the semiconductor device according to the firstembodiment;

FIG. 8 is a schematic cross-sectional view illustrating the process ofmanufacturing the semiconductor device according to the firstembodiment;

FIG. 9 is a schematic cross-sectional view illustrating the process ofmanufacturing the semiconductor device according to the firstembodiment;

FIG. 10 is a schematic diagram for explaining a function and an effectof the semiconductor device according to the first embodiment;

FIG. 11 is a schematic cross-sectional view of a main part of asemiconductor device according to a second embodiment; and

FIG. 12 is a schematic cross-sectional view of a main part of asemiconductor device according to a third embodiment.

DETAILED DESCRIPTION

Hereinafter, embodiments of the present disclosure will be describedwith reference to the drawings. Note that in the following description,the same members and the like are denoted by the same referencenumerals, and description of members and the like once described isappropriately omitted.

Here, upward in the drawings is described as “up”, and downward in thedrawings is described as “down” in order to indicate a positionalrelationship of parts and the like. Here, the terms “up” and “down” donot necessarily indicate a relationship with the direction of gravity.

Hereinafter, a case where a first conductivity type is n-type and asecond conductivity type is p-type will be exemplified.

In the following description, notations of n⁺, n⁻, p⁺, p, and p⁻indicate a relative level of an impurity concentration of each of theconductivity types. That is, n⁺ indicates that an impurity concentrationof n-type is relatively higher than n, and n⁻ indicates that theimpurity concentration of n-type is relatively lower than n. p⁺indicates that an impurity concentration of p-type is relatively higherthan p, and p⁻ indicates that the impurity concentration of p-type isrelatively lower than p. Note that n⁺ type and n⁻ type may be simplyreferred to as n type, and p⁺ type and p⁻ type may be simply referred toas p type.

(First Embodiment)

A semiconductor device according to the present embodiment includes: afirst semiconductor layer of first conductivity type; a secondsemiconductor layer of first conductivity type provided on the firstsemiconductor layer; a first semiconductor region of second conductivitytype provided on the second semiconductor layer; a second semiconductorregion of first conductivity type provided on the first semiconductorregion; a first electrode provided in a first trench, the first trenchreaching the second semiconductor layer from above the firstsemiconductor region, the first electrode facing the first semiconductorregion via a first insulating film; a second electrode provided in asecond trench, the second trench reaching the second semiconductor layerfrom above the first semiconductor region, the second electrode facingthe first semiconductor region via a second insulating film; a thirdelectrode including a first electrode portion, a second electrodeportion provided on the first electrode portion and a third electrodeportion provided on the second electrode portion, the first electrodeportion being provided between the first trench and the second trench,the first electrode portion reaching the first semiconductor region fromabove the second semiconductor region, the first electrode portion beingelectrically connected to the first semiconductor region and the secondsemiconductor region; a third semiconductor region provided between thethird electrode and the second semiconductor region provided between thefirst insulating film and the third electrode, the third semiconductorregion having a higher concentration of impurities of secondconductivity type than the first semiconductor region; a fourthsemiconductor region provided between the third electrode and the secondsemiconductor region provided between the second insulating film and thethird electrode, the fourth semiconductor region having a higherconcentration of impurities of second conductivity type than the firstsemiconductor region; and a fifth semiconductor region provided betweenthe first semiconductor region and the third electrode, the fifthsemiconductor region being provided apart from the third semiconductorregion and the fourth semiconductor region, the fifth semiconductorregion having a higher concentration of impurities of secondconductivity type than the first semiconductor region.

FIG. 1 is a schematic cross-sectional view of a semiconductor device 100according to the present embodiment. FIG. 2 is a schematiccross-sectional view of a main part of the semiconductor device 100according to the present embodiment. The semiconductor device 100 is,for example, a vertical MOSFET.

The semiconductor device 100 includes a drain layer 10, a drift layer12, a base region 14, a source region 16, a first p⁺ region 20, a secondp⁺ region 22, a third p⁺ region 24, a barrier metal 36, a drainelectrode 38, a source electrode 42, a first trench 50, a thirdinsulating film 52, an insulating film 53, a first field plate electrode54, a fifth insulating film 56, a first gate electrode 58, an interlayerinsulating film 60, a second trench 70, a fourth insulating film 72, aninsulating film 73, a second field plate electrode 74, a sixthinsulating film 76, and a second gate electrode 78.

Note that the drain layer 10 is an example of the first semiconductorlayer. The drift layer 12 is an example of the second semiconductorlayer. The base region 14 is an example of the first semiconductorregion. The source region 16 is an example of the second semiconductorregion. The first p⁺ region 20 is an example of the third semiconductorregion. The second p⁺ region 22 is an example of the fourthsemiconductor region. The third p⁺ region 24 is an example of the fifthsemiconductor region. A second electrode portion 42 b which is a part ofthe source electrode 42 is an example of the third electrode. The firstfield plate electrode 54 is an example of a fourth electrode. The firstgate electrode 58 is an example of the first electrode. The second fieldplate electrode 74 is an example of a fifth electrode. The second gateelectrode 78 is an example of the second electrode. The drain electrode38 is an example of a sixth electrode. An insulating film 53 b as theinsulating film 53 is an example of the first insulating film. Aninsulating film 73 a as the insulating film 73 is an example of thesecond insulating film.

The drain layer 10 functions as a drain of the MOSFET. The drain layer10 contains, for example, a semiconductor material of n⁺ type.

The drain electrode 38 is provided under the drain layer 10 and iselectrically connected to the drain layer 10. In other words, the drainlayer 10 is provided between the drain electrode 38 and the drift layer12. The drain electrode 38 functions as a drain electrode of the MOSFET.

The drift layer 12 is provided on the drain layer 10. The drift layer 12functions as a drift layer of the MOSFET. The drift layer 12 contains,for example, a semiconductor material of n⁻ type.

Here, an X direction, a Y direction perpendicular to the X direction,and a Z direction perpendicular to the X direction and the Y directionare defined. The drain electrode 38, the drain layer 10, and the driftlayer 12 are provided parallel to an XY plane parallel to the Xdirection and the Y direction. The Z direction is a direction in whichthe drain electrode 38, the drain layer 10, and the drift layer 12 arestacked.

The base region 14 is provided on the drift layer 12. The base region 14functions as a base of the MOSFET. The base region 14 forms a channeland allows carriers to flow between the source region 16 and the drainlayer 10 when a voltage is applied to the first gate electrode 58 or thesecond gate electrode 78. The base region 14 contains, for example, asemiconductor material of p⁻ type. The semiconductor device 100 includesbase regions 14 a, 14 b, and 14 c as the base region 14.

The source region 16 is provided on the base region 14. The sourceregion 16 functions as a source of the MOSFET. When an appropriatevoltage is applied to the first gate electrode 58 or the second gateelectrode 78, carriers flow between the source region 16 and the drainlayer 10. The source region 16 contains, for example, a semiconductormaterial of n⁺ type. The semiconductor device 100 includes sourceregions 16 a, 16 b, 16 c, and 16 d as the source region 16.

The first trench 50 is formed so as to reach the drift layer 12 fromabove the base region 14.

The second trench 70 is formed so as to reach the drift layer 12 fromabove the base region 14.

The first field plate electrode 54 is provided in the first trench 50via the third insulating film 52. The first field plate electrode 54 isprovided, for example, in order to reduce concentration of a reverseelectric field between the first gate electrode 58 and the drainelectrode 38 to increase a breakdown voltage. For example, the firstfield plate electrode 54 has a portion extending upward in a portion(not illustrated) provided in the depth direction of FIG. 1 . The firstfield plate electrode 54 is electrically connected to the sourceelectrode 42 using the upwardly extending portion. Note that how toconnect the first field plate electrode 54 to the source electrode 42 isnot limited to this connecting method. The first field plate electrode54 does not have to be provided.

The second field plate electrode 74 is provided in the second trench 70via the fourth insulating film 72. The second field plate electrode 74is provided, for example, in order to reduce concentration of a reverseelectric field between the second gate electrode 78 and the drainelectrode 38 to increase a breakdown voltage. For example, the secondfield plate electrode 74 has a portion extending upward in a portion(not illustrated) provided in the depth direction of FIG. 1 . The secondfield plate electrode 74 is electrically connected to the sourceelectrode 42 using the upwardly extending portion. Note that how toconnect the second field plate electrode 74 to the source electrode 42is not limited to this connecting method. The second field plateelectrode 74 does not have to be provided.

The third insulating film 52 is provided in the first trench 50. Thethird insulating film 52 functions as a field plate insulating film thatinsulates the first field plate electrode 54 from the drift layer 12.For example, the third insulating film 52 may be provided around thefirst field plate electrode 54 so as to cover the first field plateelectrode 54.

The insulating film 53 is provided on the third insulating film 52 inthe first trench 50. An insulating film 53 a as the insulating film 53is provided between the base region 14 a and the first gate electrode58. An insulating film 53 b as the insulating film 53 is providedbetween the base region 14 b and the first gate electrode 58. In otherwords, the first gate electrode 58 is provided in the first trench 50 soas to face the base region 14 a via the insulating film 53 a. The firstgate electrode 58 is provided in the first trench 50 so as to face thebase region 14 b via the insulating film 53 b. The insulating film 53functions as a gate insulating film that insulates the first gateelectrode 58 from the base region 14. The insulating film 53 a and theinsulating film 53 b each have a smaller film thickness than the thirdinsulating film 52 in a direction perpendicular to a direction in whichthe drain layer 10 and the drift layer 12 are stacked.

The third insulating film 52 and the insulating film 53 insulate thefirst field plate electrode 54 and the first gate electrode 58 from thedrift layer 12, the base region 14, and the source region 16.

The fourth insulating film 72 is provided in the second trench 70. Thefourth insulating film 72 functions as a field plate insulating filmthat insulates the second field plate electrode 74 from the drift layer12. For example, the fourth insulating film 72 may be provided aroundthe second field plate electrode 74 so as to cover the second fieldplate electrode 74.

The insulating film 73 is provided on the fourth insulating film 72 inthe second trench 70. An insulating film 73 a as the insulating film 73is provided between the base region 14 b and the second gate electrode78. An insulating film 73 b as the insulating film 73 is providedbetween the base region 14 c and the second gate electrode 78. In otherwords, the second gate electrode 78 is provided in the second trench 70so as to face the base region 14 b via the insulating film 73 a. Thesecond gate electrode 78 is provided in the second trench 70 so as toface the base region 14 c via the insulating film 73 b. The insulatingfilm 73 functions as a gate insulating film that insulates the secondgate electrode 78 from the base region 14. The insulating film 73 a andthe insulating film 73 b each have a smaller film thickness than thefourth insulating film 72 in a direction perpendicular to a direction inwhich the drain layer 10 and the drift layer 12 are stacked. Note thatthe insulating film 73 may be formed simultaneously in the same step asthe fourth insulating film 72, or may be formed in a different step.

The fourth insulating film 72 and the insulating film 73 insulate thesecond field plate electrode 74 and the second gate electrode 78 fromthe drift layer 12, the base region 14, and the source region 16.

The fifth insulating film 56 is provided above the first field plateelectrode 54. For example, when the third insulating film 52 is providedso as to cover the first field plate electrode 54, the fifth insulatingfilm 56 is provided on a part of the third insulating film 52. The fifthinsulating film 56 is formed of, for example, phosphosilicate glass(PSG). Note that the third insulating film 52 may be formed in a portionwhere the fifth insulating film 56 is provided, instead of the fifthinsulating film 56.

The sixth insulating film 76 is provided above the second field plateelectrode 74. For example, when the fourth insulating film 72 isprovided so as to cover the second field plate electrode 74, the sixthinsulating film 76 is provided on a part of the fourth insulating film72. The sixth insulating film 76 is formed of, for example,phosphosilicate glass (PSG). Note that the fourth insulating film 72 maybe formed in a portion where the sixth insulating film 76 is providedinstead of the sixth insulating film 76.

The first gate electrode 58 is provided on the fifth insulating film 56.The first gate electrode 58 functions as a gate of the MOSFET.

The second gate electrode 78 is provided on the sixth insulating film76. The second gate electrode 78 functions as a gate of the MOSFET.

An interlayer insulating film 60 a (an example of a seventh insulatingfilm) as the interlayer insulating film 60 is provided on the first gateelectrode 58. An interlayer insulating film 60 b (an example of aneighth insulating film) as the interlayer insulating film 60 is providedon the second gate electrode 78.

The source electrode 42 has a first electrode portion 42 a, a secondelectrode portion 42 b, a third electrode portion 42 c, a fourthelectrode portion 42 d, a fifth electrode portion 42 e (an example of aseventh electrode), a sixth electrode portion 42 f, and a seventhelectrode portion 42 g. The seventh electrode portion 42 g (an exampleof an eighth electrode) is provided over the interlayer insulating film60. The fourth electrode portion 42 d, the fifth electrode portion 42 e,and the sixth electrode portion 42 f are provided below the seventhelectrode portion 42 g so as to penetrate the interlayer insulating film60. The first electrode portion 42 a is provided below the fourthelectrode portion 42 d so as to reach the base region 14 a. The secondelectrode portion 42 b is provided below the fifth electrode portion 42e so as to reach the base region 14 b. The third electrode portion 42 cis provided below the sixth electrode portion 42 f so as to reach thebase region 14 c. The source electrode 42 functions as a source of theMOSFET. For example, the first electrode portion 42 a, the secondelectrode portion 42 b, the third electrode portion 42 c, the fourthelectrode portion 42 d, the fifth electrode portion 42 e, the sixthelectrode portion 42 f, and the seventh electrode portion 42 g areformed simultaneously. However, the first electrode portion 42 a, thesecond electrode portion 42 b, the third electrode portion 42 c, thefourth electrode portion 42 d, the fifth electrode portion 42 e, thesixth electrode portion 42 f, and the seventh electrode portion 42 g donot have to be formed simultaneously.

First p⁺ regions 20 a _(i), 20 a ₂, and 20 b which are the first p⁺regions 20 are provided between a source region 16 b and the secondelectrode portion 42 b. The source region 16 b is provided between theinsulating film 53 b and the second electrode portion 42 b. The first p⁺region 20 a ₁ is provided above a lower surface 16 b ₁ of the sourceregion 16 b. The first p⁺ region 20 a ₂ is provided below the lowersurface 16 b ₁ of the source region 16 b. The first p⁺ region 20 b isprovided below and on a side of the first p⁺ region 20 a ₂ below thelower surface 16 b ₁ of the source region 16 b. The first p⁺ regions 20a ₁, 20 a ₂, and 20 b each contain, for example, a p⁺ type semiconductormaterial. The first p⁺ region 20 b is formed by diffusion of p-typeimpurities contained in the first p⁺ regions 20 a ₁ and 20 a ₂ during aheat treatment for activating impurities. For example, the p-typeimpurity concentration of the first p⁺ region 20 b is lower than thep-type impurity concentration of each of the first p⁺ regions 20 a ₁ and20 a ₂. Note that the first p⁺ region 20 a ₁ is an example of a firstportion, and the first p⁺ region 20 a ₂ is an example of a secondportion. The lower surface 16 b ₁ of the source region 16 b is anexample of a first lower surface.

Second p⁺ regions 22 a ₁, 22 a ₂, and 22 b which are the second p⁺regions 22 are provided between a source region 16 c and the secondelectrode portion 42 b. The source region 16 c is provided between theinsulating film 73 a and the second electrode portion 42 b. The secondp⁺ region 22 a ₁ is provided above a lower surface 16 c ₁ of the sourceregion 16 c. The second p⁺ region 22 a ₂ is provided below the lowersurface 16 c ₁ of the source region 16 c. The second p⁺ region 22 b isprovided below and on a side of the second p⁺ region 22 a ₂ below thelower surface 16 c ₁ of the source region 16 c. The second p⁺ regions 22a ₁, 22 a ₂, and 22 b each contain, for example, a p⁺ type semiconductormaterial. The second p⁺ region 22 b is formed by diffusion of p-typeimpurities contained in the second p⁺ regions 22 a ₁ and 22 a ₂ during aheat treatment for activating impurities. For example, the p-typeimpurity concentration of the second p⁺ region 22 b is lower than thep-type impurity concentration of each of the second p⁺ regions 22 a ₁and 22 a ₂. Note that the second p⁺ region 22 a ₁ is an example of athird portion, and the second p⁺ region 22 a ₂ is an example of a fourthportion. The lower surface 16 c ₁ of the source region 16 c is anexample of a second lower surface.

Here, the source region 16 b extends over the first p⁺ region 20. Thesource region 16 c extends over the second p⁺ region 22.

Similarly, a p⁺ region 26 is provided between the first electrodeportion 42 a and the insulating film 53 a, and a p⁺ region 28 isprovided between the third electrode portion 42 c and the insulatingfilm 73 b.

Third p⁺ regions 24 a and 24 b which are the third p⁺ regions 24 areprovided apart from the first p⁺ region 20 and the second p⁺ region 22between the drift layer 12 and the second electrode portion 42 b. Thethird p⁺ regions 24 a and 24 b each contain, for example, a p⁺typesemiconductor material. The third p⁺ region 24 b is formed by diffusionof p-type impurities contained in the third p⁺ region 24 a during a heattreatment for activating impurities. For example, the p-type impurityconcentration of the third p⁺ region 24 b is lower than the p-typeimpurity concentration of the third p⁺ region 24 a.

Similarly, a p⁺ region 30 is provided between the first electrodeportion 42 a and the drift layer 12, and a p⁺ region 32 is providedbetween the third electrode portion 42 c and the drift layer 12.

The barrier metal 36 is provided between the source electrode 42 and thebase region 14, the source region 16, the first p⁺ region 20, the secondp⁺ region 22, the third p⁺ region 24, the p⁺ region 26, the p⁺ region28, the p⁺ region 30, the p⁺ region 32,and the interlayer insulatingfilm 60. The barrier metal 36 is a film used for preventing a reactionbetween the source electrode 42 and a semiconductor material used forthe semiconductor device 100. The barrier metal 36 contains, forexample, titanium (Ti), titanium nitride (TiN), tantalum (Ta), ortantalum nitride (TaN).

For example, as illustrated in FIG. 2 , the third p⁺ region 24 a is incontact with a barrier metal 36 a provided on a bottom surface of thesecond electrode portion 42 b. For example, as illustrated in FIG. 2 ,the first p⁺ regions 20 a ₁, 20 a ₂, and 20 b which are the first p⁺regions 20 are in contact with a barrier metal 36 b provided on a leftside surface of the second electrode portion 42 b. For example, asillustrated in FIG. 2 , the second p⁺ regions 22 a ₁, 22 a ₂, and 22 bwhich are the second p⁺ regions 22 are in contact with a barrier metal36 c provided on a right side surface of the second electrode portion 42b. A barrier metal 36 d is in contact with the fifth electrode portion42 e and the source region 16 b. A barrier metal 36 e is in contact withthe fifth electrode portion 42 e and the source region 16 c. A barriermetal 36 f is in contact with the interlayer insulating film 60 a andthe fifth electrode portion 42 e. A barrier metal 36 g is in contactwith the interlayer insulating film 60 b and the fifth electrode portion42 e. A barrier metal 36 h is in contact with the seventh electrodeportion 42 g and the interlayer insulating film 60 a. A barrier metal 36i is in contact with the seventh electrode portion 42 g and theinterlayer insulating film 60 b. Note that the barrier metal 36 a is anexample of a first barrier metal portion. The barrier metal 36 b is anexample of a second barrier metal portion. The barrier metal 36 c is anexample of a third barrier metal portion. The barrier metal 36 d is anexample of a fourth barrier metal portion. The barrier metal 36 e is anexample of a fifth barrier metal portion. The barrier metal 36 f is anexample of a sixth barrier metal portion. The barrier metal 36 g is anexample of a seventh barrier metal portion. The barrier metal 36 h is anexample of an eighth barrier metal portion. The barrier metal 36 i is anexample of a ninth barrier metal portion.

A semiconductor material used for the drain layer 10, the drift layer12, the base region 14, the source region 16, the first p⁺ region 20,the second p⁺ region 22, the third p⁺ region 24, the p⁺ region 26, thep⁺ region 28, the p⁺ region 30, and the p⁺ region 32 are, for example,silicon (Si). However, the semiconductor material used for the drainlayer 10, the drift layer 12, the base region 14, the source region 16,the first p⁺ region 20, the second p⁺ region 22, the third p⁺ region 24,the p⁺ region 26, the p⁺ region 28, the p⁺ region 30, and the p⁺ region32 may be another semiconductor material such as silicon carbide (SiC),gallium nitride (GaN), or gallium arsenide (GaAs).

When silicon is used as the semiconductor material, for example, arsenic(As), phosphorus (P), or antimony (Sb) can be used as n-type impurities,and boron (B) can be used as p-type impurities.

The first gate electrode 58, the second gate electrode 78, the firstfield plate electrode 54, and the second field plate electrode 74 eachcontain a conductive material such as polysilicon containing impurities.

The insulating film 53, the insulating film 73, the third insulatingfilm 52, the fourth insulating film 72, and the interlayer insulatingfilm 60 each contain an insulating material such as silicon oxide orsilicon nitride (SiN).

The drain electrode 38 and the source electrode 42 each contain a metalsuch as aluminum (Al).

FIGS. 3 to 9 are schematic cross-sectional views illustrating a processof manufacturing the semiconductor device 100 according to the presentembodiment.

First, the drift layer 12 is formed on the drain layer 10 by, forexample, epitaxial growth. For example, the drain layer 10 is used as asemiconductor substrate, and the drift layer 12 is formed on the drainlayer 10 by epitaxial growth. Next, the first trench 50 and the secondtrench 70 are formed in the drift layer 12 by, for example,photolithography and reactive ion etching (RIE) (FIG. 3 ).

Next, a semiconductor device in the middle of manufacture illustrated inFIG. 4 is formed by, for example, a manufacturing method disclosed inPatent Document 2 (JP 2018-046253 A).

Next, the interlayer insulating film 60 is formed on the source region16, the first gate electrode 58, and the second gate electrode 78 by,for example, CVD (FIG. 5 ).

Next, etching is performed by, for example, photolithography and RIE toform a trench 82 a, a trench 82 b, and a trench 82 c in the interlayerinsulating film 60. Next, a trench 80 a, a trench 80 b, and a trench 80creaching the base region 14 are formed under the trench 82 a, the trench82 b, and the trench 82 c, respectively, by, for example, RIE (FIG. 6 ).Note that the width of each of the trench 80 and the trench 82 formedmay be narrower as it goes downward, as illustrated in FIG. 6 .

Next, the interlayer insulating film 60 is selectively etched using achemical solution to widen the widths of the trenches 82 a, 82 b and 82c (FIG. 7 ).

Next, for example, by ion implantation of B which is an example ofp-type impurities, the first p⁺ region 20, the second p⁺ region 22, thethird p⁺ region 24, the p⁺ region 26, the p⁺ region 28, the p⁺ region30, and the p⁺ region 32 are formed. (FIG. 8 ). Next, a heat treatmentis appropriately performed in order to activate impurities.

Next, the barrier metal 36 is formed in the trench 80, in the trench 82,and on a side surface and an upper surface of the interlayer insulatingfilm 60 by, for example, sputtering (FIG. 9 ).

Next, the source electrode 42 and the drain electrode 38 are formed by,for example, CVD or physical vapor deposition (PVD). As described above,the semiconductor device according to the present embodiment isobtained.

Next, a function and an effect of the semiconductor device 100 accordingto the present embodiment will be described.

Conventionally, a structure has been used in which the base region 14 isprovided between a plurality of the source regions 16. Meanwhile, inorder to miniaturize the above structure, a structure has come to beused in which the base region 14 is provided below the source regions16, a part of the source electrode 42 (for example, the second electrodeportion 42 b) reaching the base region 14 is provided between the sourceregions 16, and the source region 16 and the base region 14 areelectrically connected to the source electrode 42.

Here, when a reverse voltage is applied to the semiconductor device 100,holes move in the base region 14. Then, the holes flow toward a part ofthe source electrode 42 reaching the base region 14. Originally, thevoltage of the base region 14 is preferably equal to the potential ofthe source electrode 42 in order to suppress element breakdown causedwhen a reverse voltage is applied. However, when a potential differenceis generated between the potential of the base region 14 and thepotential of the source electrode 42, a parasitic bipolar transistorformed by the source region 16, the base region 14, and the drift layer12 operates, and element breakdown occurs. Therefore, it has beenrequired to prevent generation of a potential difference between thepotential of the base region 14 and the potential of the sourceelectrode 42.

In order to suppress the element breakdown, it is conceivable to providethe third p⁺ region 24 having a higher p-type impurity concentrationthan the base region 14 below the second electrode portion 42 b. This isbecause the hole conductivity in the 0 third p⁺ region 24 is higher thanthe hole conductivity in the base region 14, and therefore a potentialdifference from the potential of the source electrode 42 is hardlygenerated in the base region 14.

Here, when a region having a high p-type impurity concentration isprovided in the base region 14, if p-type impurities diffuse into achannel of the MOSFET, a 5 threshold voltage V_(th) of the MOSFETincreases. Generally, there is a relationship of tradeoff between thethreshold voltage V_(th) of the MOSFET and avalanche resistance.Therefore, it has been desired to increase the avalanche resistancewhile an increase in the threshold voltage V_(th) is suppressed.

The semiconductor device 100 according to the present embodimentincludes the first p⁺ region 20 provided between the source region 16 band the second electrode portion 42 b, the first p⁺ region 20 having ahigher p-type impurity concentration than the base region 14, and thesecond p⁺ region 22 provided between the source region 16 c and thesecond electrode portion 42 b, the second p⁺ region 22 having a higherp-type impurity concentration than the base region 14. Here, the thirdp⁺ region 24 is provided apart from the first p⁺ region 20 and thesecond p⁺ region 22. The hole conductivity in each of the first p⁺region 20 and the second p⁺ region 22 is higher than the holeconductivity in the base region 14, and therefore a potential differencefrom the potential of the source electrode 42 is hardly generated in thebase region 14.

FIG. 10 is a schematic diagram for explaining a function and an effectof the semiconductor device 100 according to the present embodiment. Apoint A in the vicinity of a channel of the MOSFET in the base region14, and a point B in the vicinity of the channel of the MOSFET which iscloser to the drift layer 12 are illustrated. In FIG. 10 , “sourceregion” indicates a carrier concentration (electron concentration) inthe vicinity of a channel. In FIG. 10 , “base region No. 1” indicates acarrier concentration (hole concentration) in the vicinity of a channelwhen the first p⁺ region 20 and the second p⁺ region 22 are notprovided. In FIG. 10 , “base region No. 2” indicates a carrierconcentration (hole concentration) in the vicinity of a channel when thefirst p⁺ region 20 and the second p⁺ region 22 are provided.

The p-type impurity concentration at the point A is relatively high evenwhen the first p⁺ region 20 and the second p⁺ region 22 are notprovided. Therefore, even when the first p⁺ region 20 and the second p⁺region 22 are newly provided and the p-type impurities diffuse to thepoint A, an electron concentration at the point A is much higher thanthe hole concentration, and therefore an influence on the thresholdvoltage V_(th) is small. Meanwhile, the p-type impurity concentration atthe point B is relatively low when the first p⁺ region 20 and the secondp⁺ region 22 are not provided. When the first p⁺ region 20 and thesecond p⁺ region 22 are provided without being apart from the third p⁺region 24, the amount of p-type impurities diffusing to the point B istoo large, and the threshold voltage V_(th) increases. As a result, theavalanche resistance decreases. By providing the third p⁺ region 24apart from the first p⁺ region 20 and the second p⁺ region 22 as in thepresent embodiment, it is possible to suppress an increase in thethreshold voltage V_(th).

The first p⁺ region 20 has the first p⁺ region 20 a ₁ provided above thelower surface 16 b ₁ of the source region 16 b, and the first p⁺ region20 a ₂ and the first p⁺ region 20 b provided below the lower surface 16b 1 of the source region 16 b. The second p⁺ region 22 has the second p⁺region 22 a ₁ provided above the lower surface 16 c ₁ of the sourceregion 16 c, and the second p⁺ region 22 a ₂ and the second p⁺ region 22b provided below the lower surface 16 c ₁ of the source region 16 c.This is for making flow of holes to the second electrode portion 42 beasy by providing a region having a high p-type impurity density belowthe lower surface of the source region 16.

The source region 16 b extends over the first p⁺ region 20. The sourceregion 16 c extends over the second p⁺ region 22. This is for loweringthe potential of the source region 16 by electrically connecting thesource region 16 b and the source region 16 c to the second electrodeportion 42 b sufficiently.

The semiconductor device 100 according to the present embodiment canprovide a semiconductor device having high reliability.

(Second Embodiment)

A semiconductor device 110 according to the present embodiment isdifferent from the semiconductor device 100 according to the firstembodiment in that a first width of a first portion in a directionperpendicular to a direction in which a drain layer and a drift layerare stacked is larger than a second width of a second portion in thedirection perpendicular to the direction in which the drain layer andthe drift layer are stacked, and a third width of a third portion in thedirection perpendicular to the direction in which the drain layer andthe drift layer are stacked is larger than a fourth width of a fourthportion in the direction perpendicular to the direction in which thedrain layer and the drift layer are stacked. Here, description ofcontents overlapping with those of the first embodiment is omitted.

FIG. 11 is a schematic cross-sectional view of a main part of thesemiconductor device 110 according to the present embodiment. A firstwidth d1 of a first p⁺ region 20 a ₁ is larger than a second width d₂ ofa first p⁺ region 20 a ₂, and a third width d₃ of a second p⁺ region 22a ₁ is larger than a fourth width d₄ of a second p⁺ region 22 a ₂. Here,the width is a length in a direction parallel to the XY plane.

If a distance between a second electrode portion 42 b and a channel of aMOSFET is shortened, the resistance of holes flowing in a base region 14decreases.

However, the semiconductor device 110 according to the presentembodiment can increase the volume of a p⁺ region to reduce theresistance of holes flowing in the base region 14 without shortening thedistance between the second electrode portion 42 b and the channel ofthe MOSFET. This makes it possible to provide a semiconductor devicehaving high reliability.

(Third Embodiment)

A semiconductor device 120 according to the present embodiment isdifferent from the semiconductor device 100 according to the firstembodiment and the semiconductor device 110 according to the secondembodiment in that a second semiconductor region provided between afirst insulating film and a third electrode extends over a thirdsemiconductor region and between the third semiconductor region and thethird electrode, and a second semiconductor region provided between asecond insulating film and the third electrode extends over a fourthsemiconductor region and between the fourth semiconductor region and thethird electrode. In addition, the semiconductor device 120 according tothe present embodiment is different from the semiconductor device 100according to the first embodiment and the semiconductor device 110according to the second embodiment in that a third lower surface of thethird semiconductor region is in contact with a first semiconductorregion, and a fourth lower surface of the fourth semiconductor region isin contact with the first semiconductor region. Here, description ofcontents overlapping with those of the first and second embodiments isomitted.

FIG. 12 is a schematic cross-sectional view of a main part of thesemiconductor device 120 according to the present embodiment.

A source region 16 b extends over a first p⁺ region 20 and between thefirst p⁺ region 20 and a second electrode portion 42 b. A source region16 c extends over a second p⁺ region 22 and between the second p⁺ region22 and the second electrode portion 42 b.

In the semiconductor device 120, the first p⁺ region 20 is not incontact with a barrier metal 36 b provided on a left side surface of thesecond electrode portion 42 b.

The second p⁺ region 22 is not in contact with a barrier metal 36 cprovided on a right side surface of the second electrode portion 42 b.

Also the semiconductor device 120 according to the present embodimentcan increase the volume of a p⁺ region to reduce the resistance of holesflowing in a base region 14 without shortening a distance between thesecond electrode portion 42 b and a channel of a MOSFET. This makes itpossible to provide a semiconductor device having high reliability.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the semiconductor device describedherein may be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the devices andmethods described herein may be made without departing from the spiritof the inventions. The accompanying claims and their equivalents areintended to cover such forms or modifications as would fall within thescope and spirit of the inventions.

What is claimed is:
 1. A semiconductor device comprising: a firstsemiconductor layer of first conductivity type; a second semiconductorlayer of first conductivity type provided on the first semiconductorlayer; a first semiconductor region of second conductivity type providedon the second semiconductor layer; a second semiconductor region offirst conductivity type provided on the first semiconductor region; afirst electrode provided in a first trench, the first trench reachingthe second semiconductor layer from above the first semiconductorregion, the first electrode facing the first semiconductor region via afirst insulating film; a second electrode provided in a second trench,the second trench reaching the second semiconductor layer from above thefirst semiconductor region, the second electrode facing the firstsemiconductor region via a second insulating film; a third electrodeincluding a first electrode portion, a second electrode portion providedon the first electrode portion and a third electrode portion provided onthe second electrode portion, the first electrode portion being providedbetween the first trench and the second trench, the first electrodeportion reaching the first semiconductor region from above the secondsemiconductor region, the first electrode portion being electricallyconnected to the first semiconductor region and the second semiconductorregion; a third semiconductor region provided between the thirdelectrode and the second semiconductor region provided between the firstinsulating film and the third electrode, the third semiconductor regionhaving a higher concentration of impurities of second conductivity typethan the first semiconductor region; a fourth semiconductor regionprovided between the third electrode and the second semiconductor regionprovided between the second insulating film and the third electrode, thefourth semiconductor region having a higher concentration of impuritiesof second conductivity type than the first semiconductor region; and afifth semiconductor region provided between the first semiconductorregion and the third electrode, the fifth semiconductor region beingprovided apart from the third semiconductor region and the fourthsemiconductor region, the fifth semiconductor region having a higherconcentration of impurities of second conductivity type than the firstsemiconductor region.
 2. The semiconductor device according to claim 1,wherein the third semiconductor region has a first portion and a secondportion, the first portion is provided above a first lower surface ofthe second semiconductor region provided between the first insulatingfilm and the third electrode, and the second portion is provided belowthe first lower surface, and the fourth semiconductor region has a thirdportion and a fourth portion, the third portion is provided above asecond lower surface of the second semiconductor region provided betweenthe second insulating film and the third electrode, and the fourthportion is provided below the second lower surface of the secondsemiconductor region.
 3. The semiconductor device according to claim 2,wherein a first width of the first portion in a second directionperpendicular to a first direction in which the first semiconductorlayer and the second semiconductor layer are stacked is larger than asecond width of the second portion in the second direction, and a thirdwidth of the third portion in the second direction is larger than afourth width of the fourth portion in the second direction.
 4. Thesemiconductor device according to claim 1, wherein the secondsemiconductor region provided between the first insulating film and thethird electrode extends over the third semiconductor region, and thesecond semiconductor region provided between the second insulating filmand the third electrode extends over the fourth semiconductor region. 5.The semiconductor device according to claim 1, wherein the secondsemiconductor region provided between the first insulating film and thethird electrode extends over the third semiconductor region and betweenthe third semiconductor region and the third electrode, and the secondsemiconductor region provided between the second insulating film and thethird electrode extends over the fourth semiconductor region and betweenthe fourth semiconductor region and the third electrode.
 6. Thesemiconductor device according to claim 1, further comprising: a fourthelectrode provided below the first electrode in the first trench, thefourth electrode facing the second semiconductor layer via a thirdinsulating film,; and a fifth electrode being provided below the secondelectrode in the second trench, the fifth electrode facing the secondsemiconductor layer via a fourth insulating film.
 7. The semiconductordevice according to claim 6, wherein the first insulating film has asmaller film thickness than the third insulating film in a seconddirection perpendicular to a first direction in which the firstsemiconductor layer and the second semiconductor layer are stacked, andthe second insulating film has a smaller film thickness than the fourthinsulating film in the second direction.
 8. The semiconductor deviceaccording to claim 6, further comprising: a fifth insulating filmprovided in the first trench, the fifth insulating film being providedbetween the first electrode and the fourth electrode, the fifthinsulating film containing phosphosilicate glass (PSG); and a sixthinsulating film provided in the second trench, the sixth insulating filmbeing provided between the second electrode and the fifth electrode, thesixth insulating film containing phosphosilicate glass (PSG).
 9. Thesemiconductor device according to claim 1, further comprising a sixthelectrode, wherein the first semiconductor layer is provided between thesixth electrode and the second semiconductor layer.
 10. Thesemiconductor device according to claim 1, further comprising: a barriermetal including a first barrier metal portion provided between the fifthsemiconductor region and the third electrode, a second barrier metalportion provided between the third semiconductor region and the thirdelectrode, and a third barrier metal portion provided between the fourthsemiconductor region and the third electrode.
 11. The semiconductordevice according to claim 10, wherein the fifth semiconductor region andthe first barrier metal portion are in contact with each other, thethird semiconductor region and the second barrier metal portion are incontact with each other, and the fourth semiconductor region and thethird barrier metal portion are in contact with each other.
 12. Thesemiconductor device according to claim 10, further comprising: aseventh insulating film provided on the first electrode; an eighthinsulating film provided on the second electrode, wherein the secondelectrode portion is provided between the seventh insulating film andthe eighth insulating film, and wherein the third electrode portion isprovided above the seventh insulating film and the eighth insulatingfilm, and wherein the barrier metal includes a fourth barrier metalportion provided between the second electrode portion and the secondsemiconductor region provided between the first insulating film and thefirst electrode portion; a fifth barrier metal portion provided betweenthe second electrode portion and the second semiconductor regionprovided between the second insulating film and the first electrodeportion; a sixth barrier metal portion provided between the seventhinsulating film and the second electrode portion; a seventh barriermetal portion provided between the eighth insulating film and the secondelectrode portion; an eighth barrier metal portion provided between theseventh insulating film and the third electrode portion; and a ninthbarrier metal portion provided between the eighth insulating film andthe third electrode portion.